DP80390XP – Ultra-High-Performance 8051-Compatible 8-bit CPU IP Core

The DP80390XP is a next-generation, ultra-high-performance 8-bit soft microcontroller IP core, engineered for single-chip SoC designs requiring maximum execution efficiency, low power consumption, and full 8051 software compatibility.

Designed to operate seamlessly with fast on-chip memories and slower off-chip memory devices, DP80390XP supports up to 8 MB of linear program memory and 16 MB of linear data memory, far exceeding the addressing limitations of classic 8051 microcontrollers.

A key design objective of DP80390XP is an exceptional performance-to-power ratio, further enhanced by an integrated Power Management Unit (PMU) that enables aggressive clock and power scaling without performance loss.

100% 8051 Binary Compatibility

DP80390XP is fully binary-compatible with industry-standard 8051 microcontrollers, allowing direct reuse of legacy firmware, compilers, libraries, and toolchains. Existing 8051 software can be migrated to new ASIC or FPGA platforms without modification, while achieving an order-of-magnitude performance improvement.

Flexible System Architectures

DP80390XP is available in two system configurations to match a wide range of SoC architectures:

• Harvard architecture – separate program and data buses for maximum throughput

• von Neumann architecture – shared program and external data bus for simplified system integration

This flexibility allows system designers to optimize area, performance, or memory topology based on application requirements.

Pipelined RISC Architecture with Industry-Leading Performance

At its core, DP80390XP features a pipelined RISC microarchitecture, delivering exceptional performance within the 8-bit MCU class:

• 85–200 MIPS, depending on configuration and target frequency

• Dhrystone 2.1 performance: 11.46× to 15.55× faster than the original 80C51 at the same clock frequency

• Benchmarked using the same C compiler and identical compiler settings, ensuring objective, reproducible results

This massive performance headroom enables ultra-low-power operation, where DP80390XP can be clocked more than 10× slower than a classic 8051 implementation while delivering equivalent application performance — a decisive advantage in energy-constrained designs.

Advanced Power Management for Low-Energy SoCs

The integrated PMU (Power Management Unit) enables:

• Dynamic clock scaling

• Power-efficient operation across performance states

• Reduced thermal dissipation and EMI

• Extended battery life in portable and IoT devices

This makes DP80390XP particularly suitable for always-on, battery-powered, and energy-harvesting applications.

SoC-Ready Verification and Non-Intrusive Debugging

DP80390XP is delivered with a fully automated testbench and a comprehensive regression test suite, enabling fast IP validation and smooth integration into modern SoC design flows.

Each DP80390XP core includes built-in support for DoCD™ (Digital Core Design on-Chip Debugger) — a proprietary real-time hardware debugging system that provides full SoC visibility without disturbing application execution.

DoCD™ Debug Capabilities

• Run, halt, single-step, step-over, and instruction skipping

• Read/write access to all CPU registers, SFRs, and user-defined peripherals

• Full visibility into internal and external program and data memories

• True non-intrusive debugging of real-time systems

Unlike traditional on-chip debuggers, DoCD™ allows debugging of a live, running application with no performance impact.

Key Benefits for Design Engineers

• Ultra-high-performance 8051-compatible CPU IP

• Up to 200 MIPS in an 8-bit architecture

• 11–15× faster than classic 80C51 at equal clock

• Advanced PMU for low-power and battery-driven systems

• Large linear memory addressing (8 MB code / 16 MB data)

• Harvard or von Neumann system architectures

• Non-intrusive, real-time SoC debugging

• Fully synthesizable ASIC & FPGA-ready soft IP

Target Applications

🏭 Industrial

• Industrial controllers and PLC subsystems

• Motor control and sensor aggregation

• Field devices with long lifecycle requirements

🚗 Automotive

• Body electronics and comfort systems

• Automotive sensor hubs

• Mixed-signal automotive ASICs

🌐 IoT & Edge

• Smart sensors and meters

• IoT gateways and nodes

• Battery-powered and energy-efficient edge devices

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com

• Software in 100% compatible with 80390 & 8051 industry standards
  • LARGE mode – 8051 instruction set
  • FLAT mode – 80390 instruction set
• Pipelined RISC architecture enables to run 15.55 times faster, than the original 80C51 at the same frequency
• Up to 14.632 VAX MIPS at 100 MHz
• 24 times faster multiplication
• 12 times faster division
• 2 Data Pointers (DPTR) for faster memory blocks copying
  • Advanced INC & DEC modes
  • Auto-switch of current DPTR
• Up to 256 bytes of internal (on-chip) Data Memory
• Up to 8 MB of linear Program Memory
  • 64 kB of internal (on-chip) Program Memory
  • 8 MB external (off-chip) Program Memory
• Up to 16 MB of external (off-chip) Data Memory
  • Synchronous eXternal Data Memory (SXDM) Interface
• User programmable Program Memory Wait States
• User programmable External Data Memory Wait States
• De-multiplexed Address/Data bus, to allow easy memory connection
• Interface for additional Special Function Registers
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• 2 GHz virtual clock frequency in a 0.25u technological process
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available