SMBUS & PMBUS Master/Slave controller

DPSMBUS IP Core — Advanced I²C Module with SMBus and PMBus Support

High-Performance I²C, SMBus & PMBus Communication

The DPSMBUS IP Core from DCD-SEMI is a fully-featured I²C-based module designed for embedded systems, supporting SMBus and PMBus functionalities. It can operate in both Master (DPSMBUSM) and Slave (DPSMBUSS) modes, making it versatile for a wide range of system-on-chip (SoC), FPGA, and ASIC designs.

The DPSMBUS IP Core complies with SMBus and PMBus timing requirements for SMBSDA and SMBSCK signals, ensuring reliable data communication in multi-master environments. Advanced features include arbitration handling and clock synchronization, with built-in mechanisms to recover from a stuck SMBSCK line using minimum timeout detection (Ttimeoutmin).

High-Speed Communication

The DPSMBUS supports transmission speeds of up to 3.4 Mb/s, covering all standard SMBus and PMBus rates:

• 100 kHz (Standard Mode)

• 400 kHz (Fast Mode)

• 1 MHz (Fast Mode Plus)

Advanced Slave Mode Features

In Slave mode, DPSMBUS provides an internal FIFO buffer capable of storing up to 256 bytes, allowing efficient data handling even under high traffic conditions. Key features include:

• Monitoring of transmission status and failure points

• SMBAlert signal support for interrupt-driven notifications between Master and Slave devices

• Support for arbitration of multiple Slave devices

PMBus-Specific Functionality

The PMBus version of DPSMBUS extends capabilities to include:

• ALERT RESPONSE ADDRESS, GENERAL CALL, DEVICE DEFAULT ADDRESS, ZONE WRITE, and ZONE READ

• Group command protocol and extended command functionality

• CONTROL and WRITE PROTECT signals for enhanced device supervision

This ensures seamless integration into power management systems and other complex SMBus/PMBus networks.

Why Choose DCD-SEMI DPSMBUS IP Core

• Fully compliant with I²C, SMBus, and PMBus standards

• Operates as Master or Slave with flexible modes

• Supports 100 kHz, 400 kHz, 1 MHz, up to 3.4 Mb/s speeds

• Internal FIFO (256 bytes) for efficient Slave mode operation

• SMBAlert handling for interrupt-driven multi-device arbitration

• PMBus extended functionality, group commands, and supervision signals

• Ideal for embedded systems, SoCs, FPGA, and ASIC applications

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For technical specifications, integration support, or customization options, contact info@dcd-semi.com

• • Conforms to v3.1 of the SMBus specification and 1.3.1 PMBus specification
  • Master operation:
    • Master transmitter
    • Master receiver
  • Slave operation
    • • Slave transmitter
      • Slave receiver
  • Supports up to 3.4 Mb/s, which covers all acceptable speeds for SMBus and PMBus
  • Performs arbitration and clock synchronization
  • Multi-master system supported
  • Interrupt generation along with SMBAlert bus signal
  • Meet the requirements for SMBSDA and SMBCLK acceptable timing intervals
  • Allows operation from a wide range of input clock frequencies (built-in 8-bit timer)
  • The simple interface allows easy connection to microcontrollers
  • User-defined timings
  • DSPMBus driver supports all SMBus and PMBus communication sequences
  • Fully synthesizable
  • Static synchronous design with positive edge clocking and configurable reset
  • DSPMBUS driver has implemented CRC8 calculation required for PEC bytes

  SMBUS

  • Compatible with ALERT RESPONSE ADDRESS, and DEVICE DEFAULT ADDRESS predefined addresses
  • Implemented FIFO, which can store up to 256 bytes
  • Supports SMBAlert arbitration

  PMBUS

  • Has implemented CONTROL and WRITE PROTECT signals required for PMBus protocol
  • Compatible with ALERT RESPONSE ADDRESS, GENERAL CALL, DEVICE DEFAULT ADDRESS, ZONE WRITE, and ZONE READ predefined addresses
  • Accepts group command protocol and extended command functionality
  • Implemented FIFO, which can store up to 256 bytes