SMBUS & PMBUS Master/Slave controller

The DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities.

It can operate as a DPSMBUSM – Master and DPSMBUSS – Slave. Due to SMBus and PMBus documentation, the module meets the requirements, both for SMBSDA and SMBSCK acceptable timing intervals.

The DSPMBUS module supports arbitration and clock synchronization, which is necessary for multi-master systems. The IP Core, as it’s been suggested in the SMBus documentation, has implemented a reaction on a stuck SMBSCK signal in a low state Ttimeoutmin.

DPSMBUS supports transmission speeds up to 3.4 Mb/s, which cover all three acceptable speeds for SMBus and PMBus:

1. 100 kHz,
2. 400 kHz,
3. 1 MHz.

The DPSMBUS in the slave mode has attached internal FIFO, which can store even up to 256 bytes. It is also possible to read the status of the transmission including a step where communication failed. Except for SMBSDA and SMBSCK, there is also SMBAlert, which is defined as an interrupt signal between master and slave devices. Due to the SMBAlert handler, DPSMBUS supports arbitration of slave devices.

The DPSMBUS in PMBus version accepts ALERT RESPONSE ADDRESS, GENERAL CALL, DEVICE DEFAULT ADDRESS, ZONE WRITE, and ZONE READ predefined addresses. Also, it is possible to perform group command protocol and even extended command functionality. There are included CONTROL and WRITE PROTECT signals along with their functionality for device supervision.

DESIGN FEATURES:

All DCD’s IP Cores are technology independent which means that they are 100% compatible with all FPGA & ASIC vendors e.g.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others. 
• TSMC
• UMC
• SK Hynix
  and others.

• • Conforms to v3.1 of the SMBus specification and 1.3.1 PMBus specification
  • Master operation:
    • Master transmitter
    • Master receiver
  • Slave operation
    • • Slave transmitter
      • Slave receiver
  • Supports up to 3.4 Mb/s, which covers all acceptable speeds for SMBus and PMBus
  • Performs arbitration and clock synchronization
  • Multi-master system supported
  • Interrupt generation along with SMBAlert bus signal
  • Meet the requirements for SMBSDA and SMBCLK acceptable timing intervals
  • Allows operation from a wide range of input clock frequencies (built-in 8-bit timer)
  • The simple interface allows easy connection to microcontrollers
  • User-defined timings
  • DSPMBus driver supports all SMBus and PMBus communication sequences
  • Fully synthesizable
  • Static synchronous design with positive edge clocking and configurable reset
  • DSPMBUS driver has implemented CRC8 calculation required for PEC bytes

  SMBUS

  • Compatible with ALERT RESPONSE ADDRESS, and DEVICE DEFAULT ADDRESS predefined addresses
  • Implemented FIFO, which can store up to 256 bytes
  • Supports SMBAlert arbitration

  PMBUS

  • Has implemented CONTROL and WRITE PROTECT signals required for PMBus protocol
  • Compatible with ALERT RESPONSE ADDRESS, GENERAL CALL, DEVICE DEFAULT ADDRESS, ZONE WRITE, and ZONE READ predefined addresses
  • Accepts group command protocol and extended command functionality
  • Implemented FIFO, which can store up to 256 bytes