DOSPI

DOSPI Octal SPI IP Core — High-Speed, Low-Latency SPI Controller for Advanced SoC & FPGA Designs

The DOSPI Octal SPI IP Core is a high-performance, low-latency SPI controller engineered for next-generation SoC and FPGA architectures. Designed for demanding embedded applications, the DOSPI delivers exceptional throughput and deterministic timing, providing maximum SPI clock speeds up to CLK/2—far beyond typical SPI controllers limited to CLK/8. This makes it an ideal choice for systems requiring fast access to serial SPI memories, high-bandwidth peripherals, or real-time inter-processor communication.

Fully compatible with APB, AHB, and AXI system buses, the DOSPI integrates seamlessly into a wide range of design environments. The core supports 8-, 16-, and 32-bit processors, as well as little-endian and big-endian data formats, ensuring broad compatibility across embedded platforms. As a programmable SPI Master/Slave, it provides full control over SCK polarity, phase, and four advanced SPI clocking modes—guaranteeing interoperability with virtually any synchronous serial peripheral.

At the heart of the DOSPI is support for Single, Dual, Quad, and Octal SPI transfer modes. With Double Data Rate (DDR) clocking enabled, the IP core transfers data on both edges of the SCK signal, achieving up to 16 bits per SCK cycle in Octal DDR mode. This level of performance is crucial for high-speed SPI Flash, low-latency Execute-in-Place (XIP) systems, RAM shadowing, and any design where startup time, code throughput, or memory bandwidth is essential.

Optimized for Performance-Critical Applications

The DOSPI Octal SPI IP Core excels in:

• Execute-in-Place (XIP) architectures requiring minimal latency

• Systems performing fast Flash-to-RAM shadowing or real-time memory access

• Cost-optimized embedded platforms requiring high performance without parallel memory buses

• Inter-processor communication in multi-master topologies

• Designs requiring octal SPI flash support and maximum bandwidth utilization

Robust Reliability & Multi-Master Safety

For complex bus environments, DOSPI integrates advanced protection mechanisms, including:

• Write-collision detection

• Multi-master arbitration fault protection

• Automatic disabling of drivers during contention

• Deterministic slave selection via the dedicated Slave Select Control Register (SSCR)

This ensures stable operation in systems with shared buses, multiple masters, or safety-critical workloads.

High-Efficiency DMA Support

The DOSPI supports single-transfer and multi-transfer DMA modes, enabling:

• Zero-CPU-overhead transfers

• Continuous high-speed streaming

• Efficient integration with high-performance DMA controllers

This is essential for designs that must sustain maximum data throughput while minimizing power and processing overhead.

Customizable, Technology-Independent Design

As with all DCD-SEMI IP cores, the DOSPI is:

• Fully customizable for specific SoC or FPGA requirements

• Technology-agnostic, ready for ASIC or FPGA implementation

• Delivered with optional modifications for protocol, timing, and bus configurations

This flexibility ensures optimal fit for architectures focused on memory performance, boot-time reduction, or low-power embedded operation.

Why Engineers Choose DOSPI

If your design requires maximum SPI throughput, ultra-low latency, advanced Quad/Octal SPI support, and seamless APB/AHB/AXI integration, the DOSPI Octal SPI IP Core delivers best-in-class performance for next-generation embedded, automotive, industrial, and consumer SoC designs.

Which One to Choose DQSPI vs DOSPI

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Operates with 8, 16 and 32 bit CPUs
• Full duplex synchronous serial data transfer
• DMA support
• Support for 32, 16 and 8 bit systems
• Support for various system Bus Standards
• Single, Dual, Quad and Octal SPI transfer
• DDR support (Double Data Rate)
• Multimaster system supported
• Optional FIFO size extension (128, 256, 512B)
• Up to 7 SPI slaves can be addressed (more Slave Select Outputs can be added upon request)
  • Software Slave Select Output – SSO ‐ selection
  • Automatic Slave Select outputs assertion during each byte transfer
• System error detection
• Interrupt generation
• Various Bit rates supported
• Bit rate in fast SPI Mode ½ CLK
• Four transfer formats
• Simple CPU and DMA interface
• Fully synthesizable, static synchronous de-sign with no internal tri‐states
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus