DMESCC

DMESCC IP Core – Dual-Channel Multiprotocol Serial Controller for FPGA & ASIC

The DMESCC IP Core from DCD-SEMI is a Dual-Channel Multiprotocol Enhanced Serial Communication Controller designed for reliable integration into FPGA and ASIC designs. Optimized for use with 8-bit and 16-bit microprocessors, DMESCC provides a flexible and scalable solution for implementing both asynchronous and synchronous serial communication protocols in embedded, industrial, and telecommunications systems.

With two fully independent full-duplex channels, DMESCC enables simultaneous transmit and receive operations, ensuring deterministic performance across a wide range of serial data transfer applications.

Broad Protocol Support

DMESCC supports a comprehensive set of serial communication formats, including:

• Asynchronous serial protocols

• Synchronous byte-oriented protocols (e.g. IBM® Bisync)

• Synchronous bit-oriented protocols, such as HDLC and SDLC

In all synchronous modes, the IP Core can generate and check CRC codes, allowing designers to implement robust data integrity checking tailored to application-specific requirements.

Highly Configurable Serial Operation

Each channel of the DMESCC IP Core is independently configurable through dedicated control and status registers, enabling fine-grained protocol control. The core supports:

• Variable data sizes (5 to 8 bits per character)

• Programmable odd or even parity

• One, one-and-a-half, or two stop bits

• Character insertion and deletion

• Break and abort generation and detection

• Flexible CRC generation and checking

This configurability allows DMESCC to adapt to both legacy communication standards and modern embedded designs without hardware changes.

Dual-Channel Full-Duplex Architecture

DMESCC provides two independent full-duplex channels, each programmable for any supported asynchronous or synchronous protocol. In asynchronous mode, transmission and reception can operate independently per channel, while built-in break generation and break-detection logic enables immediate CPU notification via interrupts when exceptional conditions occur.

Microprocessor-Friendly Features

When used as a microprocessor peripheral, DMESCC offers valuable system-level capabilities, including:

• Vectored interrupts

• Polling support

• Simple handshake mechanisms

• Modem control on both channels

These features simplify firmware design and improve responsiveness in real-time systems.

Typical Applications

• Telecommunications equipment

• Industrial automation systems

• Embedded controllers

• Legacy protocol implementations

• FPGA-based SoCs requiring multiprotocol serial I/O

• Dual-Channel: A, B
• Configuration capability
• Asynchronous mode:
  • Asynchronous (x16, x32, or x64 clock
  • Isochronous (x1 clock)
• Character-Oriented mode:
  • Monosynchronous
  • Bisynchronous
  • External Synchronous
• Bit-Oriented mode:
  • ◊  SDLC/HDLC
  • ◊  SDLC/HDLC Loop
• Complete status reporting capabilities
• Receiver data FIFO and Error FIFO
• SDLC Frame FIFO
• Transmitter FIFO
• Data encoder\decoder:
  • NRZ, NRZI
  • FM0, FM1
  • Manchester (require external logic)
• Line break generation and detection
• Internal diagnostic capabilities:
  • Loop-back controls for communications link fault isolation
  • Auto Echo
  • Break, parity, overrun, framing error simulation
• Fully synchronous design with no internal tri-state buffers

Transmission modes: