DI3CS – MIPI® I3C Target (Slave)

DI3CS — Smart I3C Target (Slave)

Connectivity for Mobile, IoT, Automotive & Next-Gen Embedded Systems

The DI3CS is a high-performance MIPI® I3C Target Controller IP Core designed to bring efficient, high-speed, and low-power connectivity to modern embedded systems. Fully compliant with the MIPI I3C Basic Specification, it serves as a smart peripheral device communicating seamlessly with any I3C Master over the I3C bus.

Built as an evolution of the legacy I²C interface, the I3C protocol delivers higher data rates, improved power efficiency, dynamic addressing, and better scalability, making DI3CS an ideal choice for compact, sensor-rich applications in mobile devices, IoT nodes, automotive subsystems, industrial electronics, and wearables.

Feature-Rich, Specification-Compliant I3C Target IP

The DI3CS implements all mandatory functions defined by the I3C Basic specification, along with several advanced optional capabilities. Its architecture ensures easy integration into complex SoC, ASIC, and FPGA environments.

Key Supported Features

• Single Data Rate (SDR) and Double Data Rate (DDR) modes

• Dynamic Address Assignment (DAA) for flexible system configuration

• In-Band Interrupts (IBI) for efficient event signaling

• Hot-Join support for dynamic device insertion

• Common Command Codes (CCC) execution

• Error detection, recovery mechanisms, and Target Reset functionality

• Backward compatibility with I²C, enabling mixed-protocol environments

Optimized for High-Speed, Low-Power Embedded Designs

With its efficient implementation and flexible feature set, the DI3CS enables:

• Fast, reliable communication in data-intensive sensor networks

• Low-power operation, ideal for battery-driven IoT and wearable applications

• Robust interoperability with existing I3C ecosystems

• Future-proof performance aligned with next-generation embedded architectures

Whether you are designing mobile sensors, environmental monitors, automotive peripherals, or industrial controllers, the DI3CS IP Core ensures high bandwidth, reduced power consumption, and seamless integration.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

Why DI3CS?
With DI3CS, DCD-SEMI provides a forward-looking IP Core that enhances performance, reduces pin count and power usage, and simplifies integration across heterogeneous systems. Backed by decades of experience and top-tier technical support, DI3CS is your bridge to building connected, intelligent, and future-ready devices.

For further details, email info@dcd-semi.com

• MIPI I3C Basic Specification v1.2 compliance
• Native 32-bit CPU Interface
• Optional CPU interface wrappers (APB, AHB, AXI)
• Legacy I2C communication with 7-bit Static Address
• I3C Single Data Rate (SDR) mode
• Double Data Rate (DDR) suport
• Dynamic Adress Assigment (DAA) supprot
• Common Command Codes (CCC) execution
• In-Band Interrupts (IBI) suport
• Hot-Join (HJ) support
• Target Reset mechanism supprot
• TE0-TE6 Errors detection and recovery (SDR)
• Frame, parity, CRC, data errors detection and recovery (DDR)
• Configurable Asynchronous RX FIFO
• Configurable Asynchronous TX FIFO
• Masked interrupts