D16950

D16950 UART IP Core – High-Performance UART with 128-Byte FIFO for FPGA & ASIC

The D16950 UART IP Core from DCD-SEMI is a high-performance Universal Synchronous/Asynchronous Receiver/Transmitter (UART) designed for FPGA and ASIC integration. Delivered as a scalable bridge to APB, AHB, and AXI bus architectures, the D16950 is functionally compatible with the OX16C950 and fully backward compatible with 16450, 16550, 16650, and 16750 UART standards, while offering extended configuration and performance features.

The core supports serial communication in both standard UART mode and high-throughput FIFO mode, making it suitable for demanding embedded and SoC applications.

Deep FIFO Architecture for High Throughput

In FIFO mode, the D16950 activates internal FIFOs allowing:

• 128-byte transmit FIFO

• 128-byte receive FIFO, with an additional 3 bits of error status per received byte

This architecture significantly reduces interrupt frequency and CPU load while enabling reliable high-speed serial communication.

Comprehensive Status Reporting and Error Handling

The processor can read the complete UART status at any time during operation. Reported status information includes:

• Transfer operation state

• Parity, overrun, framing, and break errors

• FIFO conditions and interrupt sources

This ensures robust diagnostics and predictable system behavior.

Programmable Baud Rate and Clocking Flexibility

The D16950 includes a programmable baud rate generator capable of dividing a reference clock by divisors from 1 to (2¹⁶ − 1) to generate an n× clock for internal transmitter logic. The same clock can also drive receiver logic.

Additionally, data transmission can be synchronized to an external clock, connected via:

• RI pin (receiver and transmitter)

• DSR pin (receiver only)

This flexibility makes the core suitable for both synchronous and asynchronous applications.

Advanced UART Features and Flow Control

Key advanced capabilities include:

• Full MODEM control (RTS, CTS, DTR, DSR, DCD, RI)

• Programmable interrupt system to minimize CPU overhead

• Trigger-level control for FIFO read/write operations (1–127 bytes)

• Selectable autoflow control, automatically managing RTS/CTS signals

• 9-bit mode transmission via NMR register, with or without special character support

The ICR registers provide additional UART configuration options beyond legacy devices.

Optimized for SoC Integration and Multi-UART Designs

The D16950 is ideal for systems where the UART core and microcontroller share the same clock domain inside a single FPGA or ASIC. Its universal interface simplifies implementation and verification by eliminating unnecessary clock domain crossings.

The core is also well suited for standalone multi-UART designs, where multiple UART instances are implemented within one chip and driven by off-chip devices.

Verification-Ready and Technology Independent

Like all DCD-SEMI UART solutions, the D16950 includes a fully automated testbench with a comprehensive test suite, enabling straightforward validation throughout the entire SoC design flow.

The IP Core is technology-independent and can be implemented across a wide range of FPGA and ASIC process technologies.

Typical Applications

• FPGA and ASIC SoCs

• Multi-UART communication controllers

• Industrial and telecom systems

• Embedded controllers with high serial bandwidth requirements

• Legacy UART replacement with enhanced performance

Watch the D16950 presentation on DCD’s YouTube:

UART IP Core Family Comparison

The table below compares DCD-SEMI UART and serial communication IP Cores to help FPGA and ASIC design engineers quickly select the optimal solution for their project requirements.

Selection Guidelines

• Choose D16950 for high-bandwidth UART communication with minimal CPU load and legacy UART compatibility.
• Choose D8530 when classic dual-channel USART functionality and protocol flexibility are required.
• Choose DMESCC for advanced multiprotocol serial communication with enhanced control and block handling.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Software compatible with 16450, 16550,16650,16750 and 16950 UARTs
• Synchronous and Asynchronous transmission
• Configuration capability
• Supports RS232 and RS485 standards
• Separate configurable BAUD clock line
• Supports IRDA data format mode
• Majority Voting Logic
• Two modes of operation: UART mode and FIFO mode
  • In the FIFO mode transmitter and receiver are each buffered with 128 byte FIFO to reduce the number of interrupts presented to the CPU
  • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
• FIFO size – 128 Bytes
• Optional FIFO size extension to 256 or 512 Bytes
• Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• False start bit detection
• 16 bit programmable baud generator
• Independent receiver clock input
• MODEM control functions (CTS, RTS, DSR, DTR, RI, DCD)
• Programmable Hardware Flow Control through RTS and CTS
• Programmable Flow Control using DTR and DSR
• Programmable in-band Flow Control using XON/XOFF
• Programmable special characters detection
• Trigger levels for TX and RX FIFO
• Interrupts and automatic in-band and out-off-band flow control
• Fully programmable serial-interface characteristics:
  • 5-, 6-, 7-, 8- or 9-bit characters
  • Even, odd, or no-parity bit generation and detection
  • 1-, 1.5-, or 2-stop bit generation
  • Internal baud generator
  • Detection of bad data in receiver FIFO
• Clock prescaler from 1 to 31,875
• Enhanced isochronous clock option
• 9- bit data mode
• Software reset
• Complete status reporting capabilities
• Line break generation and detection. Internal diagnostic capabilities:
  • Loop-back controls for communications link fault isolation
  • Break, parity, overrun, framing error simulation
• Full prioritized interrupt system controls
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design and no internal tri-states