DDMA, Direct Memory Access

DDMA IP Core — High-Performance Four-Channel Direct Memory Access Controller

Efficient Data Transfer for CPU-Offloading and System Performance

The DDMA IP Core from DCD-SEMI is a four-channel Direct Memory Access (DMA) controller designed to optimize data transfers between memory and peripherals, significantly reducing CPU load and improving system performance in embedded systems, SoCs, and FPGA designs.

Programmed via a 32-bit or 8-bit native interface, the DDMA supports configurable data transaction sizes across a 32-bit address space, ranging from 1 byte up to 16 MB per transaction. To ensure smooth operation across peripherals with varying timing characteristics, the DDMA features a 32-bit FIFO transfer buffer with configurable depth.

Flexible Triggering and Peripheral Request Interface

Data transactions can be initiated by either hardware or software triggers:

• Hardware Trigger: Utilizes the Peripheral Request Interface (PRI), enabling external peripherals to request data transmission or reception on a specific DDMA channel.

• Software Trigger: Managed by the CPU through channel registers.

When multiple channels request transfers simultaneously, the DDMA employs a round-robin arbitration algorithm to efficiently manage channel priorities.

Four Independent Channels

The DDMA includes four configurable channels, each with dedicated configuration registers, enable bits, and status flags. Each channel supports three transfer modes:

• SINGLE: Transfers a single data item per request

• NORMAL: Transfers one block of data per request

• BLOCK: Transfers all configured data blocks per request

Data blocks can be customized in byte size and number of blocks, and each channel supports 8-, 16-, and 32-bit read/write operations, independently configurable for source and destination.

Flexible Addressing and Reload Options

The DDMA provides three addressing modes:

• INC: Increment address after each access

• DEC: Decrement address after each access

• FIXED: Maintain the same address

Additionally, it offers three source and destination address reload options:

• TRANSACTION: Reload after full transaction

• BLOCK: Reload after each block transfer

• NEVER: No reload

All address, block, and byte registers are double-buffered, ensuring that updates during active transfers only take effect after the current operation completes.

Advanced Status Flags and Interrupts

Each DDMA channel features channel status flags (BUSY, PENDING, IDLE) and transfer status flags to track the amount of data transmitted. Transfer status flags are maskable, allowing the generation of interrupts for specific transfer conditions, enhancing system responsiveness and control for real-time applications.

Why Choose DCD-SEMI DDMA IP Core

• Four independent DMA channels with dedicated registers and FIFO buffers

• Configurable transfer sizes from 1 byte to 16 MB

• Supports 8-, 16-, and 32-bit read/write operations

• Flexible addressing and reload modes for source and destination

• Hardware and software triggers with round-robin arbitration

• Maskable transfer status flags for interrupt generation

• Ideal for high-performance embedded systems, SoCs, and FPGA designs

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For technical details, integration support, or customization options, contact info@dcd-semi.com

• 32-bit or 8-bit internal registers access
• 32-bit transmission address range
• Transaction size from 1B up to 16MB
• Four transmission channels
• Round-robin arbitration
• Data buffer with configurable size
• For each channel:
  • Enable bit
  • Software transmission request
  • Peripheral request interface:
    • Transmission request
    • Single data transmission request
    • Reception request
    • Single data reception request
    • Configurable request clear signal
  • Transfer status flags:
    • Transaction finished
    • Block finished
    • Single data finished
  • Transfer status flags maskable interrupts
  • Three transfer modes:
    • SINGLE
    • NORMAL
    • BLOCK
  • Independently configurable source and destination data width:
    • 32-bits
    • 16-bits
    • 8-bits
  • Configurable source and destination base addresses
  • Three addressing modes: INC, DEC, FIXED
  • Three sources and destination address reload options each:
    • TRANSACTION
    • BLOCK
    • NEVER
  • Transaction divided into blocks
  • Configurable transfer size: including amount of blocks and blocks size
  • Double-buffered address, block, and byte registers
• Available DMA interface wrappers:
  • Native 32-bit interface
  • AMBA – APB / AHB / AXI
• Software reset
• Configurable hardware reset
• Fully synthesizable
• No internal tri-states