DFPIC166X

The DFPIC166X is a low-cost, high performance, 8-bit, fully static soft IP Core. The core was designed with a special concern about low power consumption, assuring the best power use, price and performance combination available on the IP core market. The DFPIC166X soft core is software compatible with industry standard PIC 16XXX Microcontrollers. It implements an enhanced Harvard architecture (separate instruction and data memories) with independent address and data buses. 14-bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The advantage of this architecture is that the instruction fetch and memory transfers can be overlapped by multi stage pipeline, so that the next instruction can be fetched from program memory while the current instruction is executed with data from the data memory. The DFPIC166X architecture is 2 times faster compared to the standard architecture. The DFPIC166X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power, remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode makes this IP core perfect for applications where the power consumption aspect is critical. The DFPIC166X is delivered with fully automated test bench and complete set of tests,  allowing easy package validation at each stage of SoC design flow. Each DCD’s PIC Core has a built-in support for a Hardware Debug System called DoCD™. It is a real-time hardware debugger which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, SFRs, user’s defined peripherals, data and program memories.

• Software compatible with PIC16C6X industry standard
• Harvard RISC architecture
  • 2 times faster compared to original implementation
• 35 instructions
• 14 bit wide instruction word
• Up to 32 kB of internal Data Memory
• Up to 64K bytes of Program Memory
• Configurable hardware stack
• Power saving SLEEP mode
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Technology independent HDL Source Code
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available