DFPIC1655X

The DFPIC1655X is a low-cost, high-performance, 8-bit, fully static soft IP Core, intended to operate with fast memory. The core is designed with a special concern about low power consumption in combination with high performance. The DFPIC1655X is the software compatible with industry-standard PIC 16XXX Microcontrollers. It has a modified RISC architecture (2 times faster than the original implementation). It has enhanced core features, a configurable hardware stack, and multiple internal and external interrupt sources. Separate instruction and data buses allow a 14-bit wide instruction word with separate 8-bit wide data. The power-down SLEEP mode allows you to reduce power consumption significantly and “wake up” the controller through several external and internal interrupts and resets. An integrated Watchdog Timer with its own dedicated clock signal provides protection against software lock-up. The DFPIC1655X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power remote transmitters/receivers, pointing devices, and telecom processors. Built-in power save mode and small area use in programmable devices, make this IP core perfect for applications with space and power consumption limitations. The DFPIC1655X is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Each DCD’s PIC Core has built-in support for a Hardware Debug System called DoCD™. It is a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of a microcontroller, including all registers, and SFRs, including user-defined peripherals, data, and program memories.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others. 
• TSMC
• UMC
• SK Hynix
  and others.

• Software compatible with PIC16C55X industry standard
• Harvard RISC architecture
  • 2 times faster, compared to original implementation
• 35 instructions
• 14 bit wide instruction word
• Up to 32 kB of internal Data Memory
• Up to 64K bytes of Program Memory
• Configurable hardware stack
• Power saving SLEEP mode
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Technology independent HDL Source Code
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available