LIN with UART half-duplex enhanced functionality
LIN Bus Controller
DCD-SEMI believes that even though something may be small or slow, it can still offer maximal efficiency and ultimate reliability. That’s why our DLIN with UART half-duplex enhanced functionality controller supports transmission speeds between 1kb/s and 20kb/s, which allows to transmit and receive LIN messages compatible to:
- LIN 1.3,
- LIN 2.1
- and the newest LIN 2.2A
DLIN bridge to APB, AHB, and AXI bus, is a softcore of the Local Interconnect Network (LIN). This interface is a serial communication protocol, primarily designed for automotive applications. Compared to the CAN, The LIN is slower, but thanks to its simplicity, it is much more cost-effective. Our Core is ideal for communication in intelligent sensors and actuators, where the bandwidth and versatility of the CAN is not required. The DLIN core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as a master or slave LIN node, depending on a work mode determined by the microprocessor/microcontroller. DCD’s controller supports transmission speeds between 1 and 20kb/s, which allows it to transmit and receive LIN messages compatible with LIN 1.3., LIN 2.1, and the newest 2.2A specification. The reported information status includes the type and condition of transfer operations performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). Our Core includes a programmable timer that allows for detecting timeout and synchronization errors. The DLIN is described at the RTL level, empowering the target use in FPGA and ASIC technologies.
Watch the DLIN presentation on DCD’s You Tube:
ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.
- Altera / Intel,
- Xilinx / AMD,
- Microsemi / Microchip,
- SK Hynix
- Conforms with LIN 1.3, LIN 2.1 and LIN 2.2A specification
- LIN with UART half-duplex enhanced functionality
- Automatic LIN Header handling
- Automatic Re-synchronization
- Data rate between 1Kbit/s and 20 Kbit/s
- Master and Slave work mode
- Time-out detection
- Extended error detection
- “Break-in-data” support
- Available system interface wrappers:
- AMBA – APB / AHB / AXI Lite Bus
- Altera Avalon Bus
- Xilinx OPB Bus
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