DMAC-RMII
10/100 Mb Media Access Controller with RMII
Description
DMAC-RMII IP Core — High-Performance Ethernet MAC Bridge for Embedded Systems
Hardware Implementation of IEEE 802.3 Ethernet MAC Protocol
The DMAC-RMII IP Core from DCD-SEMI is an innovative hardware solution bridging APB, AHB, and AXI buses with Ethernet RMII interfaces. Designed for embedded systems, SoCs, and FPGA applications, this IP Core enables full network functionality in conjunction with an external PHY device, allowing seamless transmission and reception of Ethernet frames.
Key Features
-
IEEE 802.3-compliant MAC protocol for robust Ethernet communication
-
Supports 10/100 Mbit/s speeds in half- and full-duplex modes
-
Compatible with 8-, 16-, and 32-bit processors
-
Handles both little-endian and big-endian byte formats
-
Provides static PHY IC configuration for simplified integration
-
Technology-independent design, deployable across multiple process technologies
-
Ideal for embedded systems, IoT devices, automotive networks, and industrial applications
Why Choose DCD-SEMI DMAC-RMII IP Core
-
Seamless bridge between processor buses and Ethernet networks
-
Supports a wide range of processor architectures and data bus widths
-
Fully compatible with IEEE 802.3 standards
-
Flexible and technology-agnostic design for ASIC, FPGA, and SoC integration
-
Reliable full/half duplex communication at 10 or 100 Mbps
Enable fast, reliable, and standards-compliant Ethernet connectivity in your embedded designs with DCD-SEMI’s DMAC-RMII IP Core.
Watch the DMAC-RMII presentation on DCD’s YouTube:
ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.
For detailed specifications, integration support, or customization, contact info@dcd-semi.com
Key features
- Conforms to IEEE 802.3-2002 specification
- Configurable width CPU interface with little or big endianess:
- 8-bit
- 16-bit
- 32-bit
- Simple interface allows easy connection to CPU
- Narrow address bus (4 bits) with indirect I/O interface for transmitted and received data dual port memories
- Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs
- Reduced Media Independent Interface (RMII) for connection to external 10/100 Mbps PHY transceivers
- Supports full and half duplex operation at 10 Mbps or 100 Mbps
- CRC-32 algorithm:
- calculates the FCS nibble at a time
- automatic FCS generation and checking
- able to capture frames with CRC errors if required
- Dynamic PHY configuration by STA management interface
- Early receive and transmit interrupts to increase data throughput
- Programmable MAC address
- Promiscuous mode support
- Allows operation from a wide range of input bus clock frequencies
- Fully synthesizable
- Static synchronous design
- Positive edge clocking
- No internal tri-states
- Lite design, small gate count and fast operation
- Scan test ready
- Available system interface wrappers:
- AMBA – APB / AHB / AXI Bus
- Altera Avalon Bus
- Xilinx OPB Bus
Similar products
DMAC IP Core — IEEE 802.3 Ethernet MAC Bridge for Embedded Systems High-Performance Ethernet MAC Bridge for APB, AHB, and...
Conforms to IEEE 802.3-2002 spec
Configurable width CPU interface
Simple interface=easy connection to CPU
DUSB2 – Full/High-Speed USB 2.0 Peripheral Controller IP Core The DUSB2 is a hardware implementation of a USB 2.0 full/high-speed...
Interfaces to the UTMI bus
Contains the USB PID
Supports FS and HS
DUSB2-ULPI – Full/High-Speed USB Peripheral Controller IP Core The DUSB2-ULPI is a hardware implementation of a USB 2.0 full/high-speed peripheral...
Strictly conforms to the USB v2.0 spec
Even more conforms to the ULPI v2.0
Contains USB PID