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D2694

Quad UART Core with FIFO

Description

D2694 Quad UART IP Core – High-Performance Multi-Channel UART for FPGA & ASIC

The D2694 from DCD-SEMI is a Quad-channel Universal Asynchronous Receiver/Transmitter (UART) soft core, software-compatible with SC2694, designed for seamless integration into APB, AHB, and AXI bus architectures. This high-performance core is ideal for multi-UART embedded systems, terminal clusters, and communication-intensive FPGA/ASIC designs.

Four Full-Duplex UART Channels

The D2694 provides:

  • Four independent full-duplex UART channels in a single core

  • 8-character receive and transmit FIFOs per channel for efficient buffering

  • Watchdog timers for each receiver channel to ensure reliable data reception

  • Mode register configuration and extended baud rate support for each channel

This allows engineers to implement high-throughput, low-latency serial communication in complex multi-channel systems.

Flexible Baud Rate & Clocking

Each UART channel supports independent operating speeds, configurable via:

  • 27 fixed baud rates

  • 16× clock derived from a programmable counter/timer

  • External 1× or 16× clock input

This flexible clocking mechanism enables dual-speed channel applications, making the D2694 ideal for clustered terminal systems, industrial communication, and multi-UART interfaces.

Programmable Interrupts and Modem/DMA Support

  • Independent transmitter and receiver interrupts programmable to application requirements

  • Supports polled or interrupt-driven operation

  • Integrated modem interface and DMA capability

  • Reduces CPU load while ensuring robust and reliable data handling

Key Features

  • Quad-channel UART core compatible with SC2694

  • Independent baud rate and mode configuration per channel

  • 8-character FIFO for transmit and receive paths

  • Watchdog timers for data reliability

  • Supports modem control and DMA interface

  • Compatible with APB, AHB, and AXI bus architectures

  • Fully technology-independent for FPGA or ASIC implementation

Ideal Applications

  • High-throughput multi-UART embedded systems

  • Terminal clusters and industrial serial communication networks

  • Multi-channel FPGA/ASIC UART integration

  • Legacy SC2694 replacement or upgrade solutions

Verification-Ready and Technology Independent

Like all DCD-SEMI UART cores, D2694 comes with:

  • Fully automated testbench

  • Comprehensive validation suite for SoC integration

  • Technology-independent design for implementation across FPGA and ASIC processes

 

Feature / IP Core D2692 D2694 D2698
Core Type Dual UART (DUART) Quad UART (QUART) Octal UART (OUART)
Channels 2 full-duplex 4 full-duplex 8 full-duplex
FIFO Size 8-character RX/TX 8-character RX/TX 8-character RX/TX
Watchdog Timer Yes, per receiver Yes, per receiver Yes, per receiver
Mode Register 0 Yes Yes Yes
Extended Baud Rate Yes Yes Yes
Programmable Interrupts Receiver & transmitter Receiver & transmitter Receiver & transmitter
Modem Interface Yes Yes Yes
DMA Support Yes Yes Yes
Independent Channel Speed Yes Yes Yes
Clocking Options Fixed, 16× derived, external Fixed, 16× derived, external Fixed, 16× derived, external
Polled / Interrupt Operation Supported Supported Supported
Software Compatibility SC26C92, SCC2692, SCN2681 SC2694 SC2698
Key Applications Dual-speed terminals, embedded systems Multi-UART clusters, industrial systems High-density multi-UART systems, telecom, gateways
Bus Interfaces APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI
Technology Independence Yes Yes Yes

Notes:

  • D2692: Dual-channel UART for simpler embedded applications or legacy SC26C92 replacement.

  • D2694: Quad-channel UART suitable for clustered terminals or medium multi-UART systems.

  • D2698: Octal UART designed for high-density, high-throughput serial communication applications.

 

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

 

Feature / IP Core D16450 D16550 D16750 D16752 D16950 D8530 DMESCC D26C92 DμART D2692 D2694 D2698
Core Type Classic UART FIFO-based UART High-performance UART Dual-channel high-performance UART High-throughput UART Dual-channel USART Dual-channel multiprotocol serial controller Dual-channel UART / DUART Lightweight soft UART Dual UART (DUART) Quad UART (QUART) Octal UART (OUART)
Channels 1 1 1 2 1 2 2 2 1 2 4 8
UART Compatibility 16450 / TL16C450 16550 / TL16C550A 16750 / TL16C750 16752 / TL16C752 16450–16750 + OX16C950 Zilog 8530–compatible Enhanced ESCC-compatible SC26C92 / SCC2692 / SCN2681 compatible Generic soft UART SC26C92 / SCC2692 compatible SC2694 SC2698
Supported Modes Asynchronous Asynchronous & FIFO Asynchronous & FIFO Asynchronous & FIFO, dual-channel Asynchronous & synchronous Asynchronous & synchronous Asynchronous & synchronous Asynchronous & FIFO Asynchronous Asynchronous & FIFO Asynchronous & FIFO Asynchronous & FIFO
FIFO Support ❌ No FIFO ✅ 16-byte FIFO ✅ 512-byte FIFO ✅ 64-byte FIFO per channel ✅ 128-byte FIFO Optional / limited Optional / configurable ✅ 8-character RX/TX FIFO per channel ❌ No FIFO ✅ 8-character RX/TX FIFO ✅ 8-character RX/TX FIFO ✅ 8-character RX/TX FIFO
FIFO Trigger Levels — Configurable Programmable (1–512) Programmable per channel Programmable (1–127) — — Programmable per channel — Programmable per channel Programmable per channel Programmable per channel
CPU Load High Medium Low Low Low Medium Medium Medium Low Medium Medium Medium
Error Reporting Parity, framing, overrun, break Parity, framing, overrun, break Parity, framing, overrun, break Parity, framing, overrun, break, idle Parity, framing, overrun, break Parity, CRC, abort Parity, CRC, abort Parity, framing, overrun, break Overrun, framing Parity, framing, overrun, break Parity, framing, overrun, break Parity, framing, overrun, break
CRC Generation / Check No No No No No Yes (sync modes) Yes (sync modes) No No No No No
Modem Control Full Full Advanced autoflow Hardware/software flow control, TCR Advanced autoflow Yes (both channels) Yes (both channels) Yes, DMA & modem interface Optional via software Yes Yes Yes
Interrupt System Programmable Programmable Advanced programmable Programmable, FIFO RDY register Advanced programmable Programmable Programmable Programmable, independent per channel Lightweight programmable Programmable Programmable Programmable
DMA Support Interrupt-optimized Interrupt-optimized Yes Yes Yes Yes Yes Yes Optional Yes Yes Yes
Clocking Options Internal BRG Internal BRG Internal / external Internal / external Internal / external Internal BRG Internal BRG Independent programmable clock, external or 16× derived Internal / external programmable Fixed, 16× derived, external Fixed, 16× derived, external Fixed, 16× derived, external
Special Features Legacy compatibility Configurable FIFO & Modem Deep FIFO (512B), autoflow, 16450 modes Dual-channel, FIFO RDY register, hardware/software flow control, TCR Deep FIFO, 9-bit mode, synchronous Legacy protocol support (HDLC, SDLC) Enhanced block transfer, vectored interrupts Independent channel baud rates, watchdog timers, dual-speed operation Lightweight, flexible baud rate, minimal CPU load, standalone or integrated use Dual-channel independent speed, watchdog timers Quad-channel, independent baud rates, multi-UART cluster support Octal-channel, independent baud rates, high-density multi-UART system
Typical Applications Legacy UART replacement FIFO-based legacy upgrade High-throughput UART, legacy replacement Dual-channel embedded UART, TL16C752 replacement Telecom, industrial gateways Telecom, LAN, industrial serial Communications controllers, protocol engines Dual-speed terminals, embedded dual UART systems Embedded soft UART, low-resource FPGA/ASIC designs Dual-speed terminals, embedded dual UART systems Multi-UART clusters, industrial systems High-density multi-UART systems, telecom, gateways
Bus Interfaces APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI
Technology Independence Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Download full specification

D2694 ASIC
D2694 INTEL FPGA
D2694 LATTICE
D2694 MICROSEMI
D2694 XILINX

Key features

KEY FEATURES

  • Software compatible with SC28C94 UARTs
  • Configuration capability
  • Dual full-duplex independent asynchronous receiver/transmitters
  • 8 character FIFOs for each receiver and transmitter
  • Programmable data format:
    • 5 to 8 data bits plus parity
    • Odd, even, no parity or force parity
    • 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
  • 16-bit programmable Counter/Timer
  • Programmable baud rate for each receiver and transmitter selectable from:
    • 27 fixed rates: 50 to 230.4k baud
    • Other baud rates to 230.4k baud at 16X
    • Programmable user-defined rates derived from a programmable counter/timer
    • External 1X or 16X clock
  • Parity, framing, and overrun error detection
  • False start bit detection
  • Line break detection and generation
  • Programmable channel mode:
    • Normal (full-duplex)
    • Automatic echo
    • Local loopback
    • Remote loopback
    • Multidrop mode (also called ‘wake-up’ or ‘9-bit’)
  • Multi-function 7-bit input port:
    • Can serve as clock, modem, or control inputs
    • Change of state detection on four inputs
  • Multi-function 8-bit output port:
    • Individual bit set/reset capability
    • Outputs can be programmed to be status/interrupt signals
    • FIFO states for DMA and modem interface
  • Versatile interrupt system:
    • Single interrupt output with eight maskable interrupting conditions
    • Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
    • Each FIFO can be programmed for four different interrupt levels
    • Watch dog timer for each receiver
  • Maximum data transfer rates: 1X – 1Mb/sec, 16X – 1Mb/sec
  • Automatic wake-up mode for multidrop applications
  • Start-end break interrupt/status
  • Detects break which originates in the middle of a character
  • Power down mode
  • Receiver timeout mode
  • Available system interface wrappers:
    • AMBA – APB / AHB / AXI Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus

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