D6803
8-bit Microcontroller
Description
The D6803 is a synthesizable SOFT Microcontroller IP Core, fully compatible with the Motorola MC6803. It can be used as a direct replacement for MC6803 Microcontrollers. In the standard configuration, the core has major peripheral functions integrated on-chip. An asynchronous serial communications interface (SCI) is included, as well as the main 16-bit, three-function programmable timer. A software-controlled power-saving mode – WAIT is available to save additional power. This mode makes the D6803 IP Core especially attractive for automotive and battery-driven applications. DCD’s IP Core is fully customizable – delivered in the exact configuration to meet your requirements. There is no need to pay extra for unused features and wasted silicon. The IP Core comes with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. It has built-in support for DCD’s Hardware Debug System called DoCD™ – it is a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, and SFRs, including user-defined peripherals and data and program memories.
DESIGN FEATURES:
ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.
- Altera / Intel,
- Xilinx / AMD,
- Lattice,
- Microsemi / Microchip,
and others. - TSMC
- UMC
- SK Hynix
and others.
Key features
- Cycle compatible with original implementation
- Software compatible with 6803 industry standard
- I/O Wrapper making it pin compatiblecore
- Power saving mode: WAIT
- Fully synthesizable
- Static synchronous design
- No internal tri-states
- Scan test ready
- USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available
IP Core | Architecture type | Memory space | DoCD | UART (SCI) | SPI M/S | IO Ports | Watchdog Timer | Timer | Compare / Capture | Pulse accumulator | READY pin | Chip Selects | Gatecount |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DF6808 | fast | 64k | 4 | 1 | 2/2 | - | 8300 | ||||||
DF6805 | fast | 64k | 4 | 1 | 2/2 | - | 7000 | ||||||
D6802 | legacy | 64k | - | - | - | - | - | ||||||
D6803 | legacy | 64k | 4 | 1 | + | - | 6000 | ||||||
DF6802 | fast | fast | - | - | - | - | - | ||||||
DF6803 | fast | 64k | 4 | 1 | + | - | - | ||||||
DF6811F | fast | 64k | 7 | 1 | 5/4 | - | 14000 | ||||||
DF6811E | fast | 64k | 5 | 1 | 5/4 | - | 12000 | ||||||
DF6811K | fast | 1M | 10 | 3 | 13/6 | - | 21000 | ||||||
D68HC11E | legacy | 64k | 5 | 1 | 5/4 | - | 13000 | ||||||
D68HC11F | legacy | 64k | 7 | 1 | 5/4 | 4 | 13500 | ||||||
D68HC11K | legacy | 1M | 10 | 3 | 13/6 | 4 | 21000 |
Features
DoCD Debugger
Power of Innovation is our primary target. That’s why our R&D focuses on every single IP Core detail. As a result of that concern, some unique solutions were born. One of them is the 68XX on-Chip Debugger (DoCD™), which is a complete debugging system dedicated for all 68XX Cores offered by DCD.
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