The D68HC11F is a synthesisable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard. It can be used as a direct replacement for the 68HC11F1 Microcontrollers.
In the standard configuration, the core has integrated on-chip major peripheral functions. An asynchronous serial communications interface (SCI) and separate synchronous serial peripheral interface (SPI) are included. The main 16-bit, free-running timer system, contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem, can count external events or measure external periods. Self-monitoring on-chip circuitry is included to protect the D68HC11F against system errors. The Computer Operating Properly (COP) watchdog system, protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt, if illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP, are available to conserve additional power. These modes make the D68HC11F IP Core especially attractive for automotive and battery-driven applications.
The D68HC11F Microcontroller Core can be equipped with the ADC Controller, allowing use of external ADC Controller with standard ADC software. The ADC Controller makes external ADC’s visible as internal ADC’s in original 68HC11F1 Microcontrollers.
The D68HC11F has a built-in, real time hardware on chip debugger – the DoCDTM, allowing easy software debugging and validation.
The Core is fully customizable – it is delivered in the exact configuration to meet user’s requirements. There is no need to pay extra for unused features and wasted silicon. It includes fully automated test bench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.
Each of the DCD’s D68HC11F Core, has built-in support for DCD Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC). Unlike other on-chip debuggers, the DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories.

Key features

  • Cycle compatible with original implementation
  • Software compatible with 68HC11 industry standard
  • I/O Wrapper making it pin-compatible core
  • SFR registers remapped to any 4KB memory page
  • Two power saving modes: STOP, WAIT
  • Fully synthesizable
  • Static synchronous design
  • No internal tri-states
  • Scan test ready
  • USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available
IP Core Architecture type Memory space DoCD UART (SCI) SPI M/S IO Ports Watchdog Timer Timer Compare / Capture Pulse accumulator READY pin Chip Selects Gatecount
DF6808 fast 64k 4 1 2/2 - 8300
DF6805 fast 64k 4 1 2/2 - 7000
D6802 legacy 64k - - - - -
D6803 legacy 64k 4 1 + - 6000
DF6802 fast fast - - - - -
DF6803 fast 64k 4 1 + - -
DF6811F fast 64k 7 1 5/4 - 14000
DF6811E fast 64k 5 1 5/4 - 12000
DF6811K fast 1M 10 3 13/6 - 21000
D68HC11E legacy 64k 5 1 5/4 - 13000
D68HC11F legacy 64k 7 1 5/4 4 13500
D68HC11K legacy 1M 10 3 13/6 4 21000


DOCD Debugger

Power of Innovation is our primary target. That’s why our R&D focuses on every IP Core detail. As a result of that anxiety there have been some unique solutions born. On of them is the PIC on-Chip Debugger (DoCDTM), which is complete debugging system, dedicated for for all the 68XX Cores offered by DCD.

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DOCD Debugger

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