DF6808

The DF6808 is an advanced, 8-bit, MCU IP Core with highly sophisticated, on-chip peripheral capabilities. The DF6808 soft core is binary-compatible with the industry standard Motorola 68HC08 8-bit microcontroller. It can achieve a performance of 45 – 100 million instructions per second. The DF6808 has a FAST architecture that is 3.2 times faster compared to the original implementation. In the standard configuration, the core has major peripheral functions integrated on-chip. The DF6808 Microcontroller Core contains a full-duplex UART – Asynchronous Serial Communication Interface (SCI) and Synchronous Serial Peripheral Interface (SPI). The main 16-bit, free-running timer system has two input capture lines and two output-compare lines. Self-monitoring circuitry is included on-chip, to protect against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP are available to preserve additional power. These modes make the DF6808 IP Core especially attractive for automotive and battery-driven applications. The DF6808 is fully customizable – it is delivered in the exact configuration to meet your requirements. There is no need to pay extra for unused features and wasted silicon. It includes a fully automated test bench with a complete set of tests, allowing easy package validation, at each stage of the SoC design flow. Each DCD’s DF68XX Core has built-in support for a proprietary Hardware Debug System called DoCD™. It’s a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike the other on-chip debuggers the DoCD™ enables non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, and SFRs, including user-defined peripherals, data, and program memories.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.

• TSMC
• UMC
• SK Hynix
  and others.

• FAST architecture – 3.2 times faster than the original implementation
• Software compatible with 68HC08 industry standard
• Configurable Harvard or Von Neumann architectures
• 11 times faster multiplication
• 64 bytes of System Function Registers space (SFRs)
• Up to 64K bytes of Data Memory
• Up to 64K bytes of Code Memory
• De-multiplexed Address/Data Bus to allow easy memory connection
• Two power saving modes: STOP, WAIT
• Ready pin allows Core to operate with slow program and data memories.
• Fully synthesizable
• Static synchronous design
• No internal reset generator or gated clock
• Positive edge clocking and no internal tri-states
• Scan test ready
• 800 MHz of virtual clock frequency compared to original implementation
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available