DF6811F

DF6811F – High-Performance 68HC11F-Compatible 8-bit MCU IP Core

The DF6811F is a high-performance, 8-bit microcontroller IP Core, fully binary-compatible with the industry-standard Motorola 68HC11F MCU. Designed as a modern drop-in replacement for legacy 68HC11F devices, DF6811F enables seamless migration of existing software while delivering significantly higher performance, lower power consumption, and full SoC-level customization.

At the heart of DF6811F is DCD-SEMI’s FAST CPU architecture, delivering up to 4× higher performance compared to the original 68HC11F implementation. This allows designers to achieve higher throughput at lower clock frequencies, resulting in improved efficiency and reduced power consumption.

Key Features of DF6811F IP Core

• 100% binary compatibility with Motorola 68HC11F

• Up to 4× performance improvement with FAST architecture

• Integrated on-chip peripherals in standard configuration

• FPGA and ASIC-ready soft IP Core

• Long-term availability for industrial and automotive designs

Integrated Peripherals and Interfaces

The DF6811F includes a rich set of on-chip peripherals, matching and extending the original 68HC11F functionality:

• Two serial interfaces

  • Asynchronous Serial Communication Interface (SCI)

  • Synchronous Serial Peripheral Interface (SPI)

• Advanced 16-bit free-running timer system

  • 3 input capture lines

  • 5 output compare channels

  • Real-Time Interrupt (RTI) support

• 8-bit pulse accumulator

  • Counts external events

  • Measures external signal periods

Reliability, Safety, and Power Management

DF6811F integrates multiple hardware mechanisms to ensure robust operation in safety-critical environments:

• Computer Operating Properly (COP) watchdog for software fault detection

• Illegal opcode detection generating a non-maskable interrupt (NMI)

• Self-monitoring circuitry to protect against system errors

For power-sensitive designs, DF6811F supports two software-controlled low-power modes:

• WAIT mode

• STOP mode

These features make the DF6811F an excellent choice for automotive, industrial, and battery-powered applications.

External ADC Support with Software Transparency

The DF6811F Microcontroller Core can be equipped with an ADC Controller, enabling seamless integration of an external ADC while maintaining full software compatibility with original 68HC11F ADC firmware. External ADCs appear to software as internal ADC peripherals, eliminating the need for code modifications.

Fully Customizable Soft IP – No Wasted Silicon

The DF6811F is delivered in an exact, application-specific configuration, allowing designers to include only the required features:

• No unused peripherals

• No unnecessary logic

• Optimized silicon area and cost

This pay-only-for-what-you-use model makes DF6811F ideal for both high-volume and specialized designs.

Advanced Debug with DoCD™ Hardware Debug System

Each DF6811F Core includes built-in support for DoCD™, DCD-SEMI’s non-intrusive, real-time hardware debug system. DoCD™ enables full visibility and control of the entire System-on-Chip:

• Halt, run, step into, or skip instructions

• Read/write all registers and SFRs

• Debug user-defined peripherals

• Access program and data memory in real time

Unlike traditional on-chip debuggers, DoCD™ does not disturb the running application, making it ideal for real-time and safety-critical systems.

Why Choose DF6811F?

DF6811F is the fastest, safest, and lowest-risk way to modernize 68HC11F-based designs—without rewriting a single line of code.

DF6811F vs Original 68HC11F comparison table:

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com

• FAST architecture, 4 times faster than the original implementation
• Software compatible with 68HC11 industry standard
• 10 times faster multiplication
• 16 times faster division
• 256 bytes of remapped System Function Registers space (SFRs)
• De-multiplexed Address/Data Bus, to allow easy memory connection
• Core can also be used without I/O wrapper, so each peripheral functions pins will be separated from I/O ports lines.
• Two power saving modes: STOP, WAIT
• Ready pin allows Core to operate with slow program and data memories.
• Fully synthesizable clock
• Static synchronous design
• No internal reset generator or gated clock
• Positive edge clocking and no internal tri-states
• Scan test ready
• 1 GHz of virtual clock frequency compared to the original implementation
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available