DF6805

The DF6805 is an advanced 8-bit MCU IP Core with highly sophisticated, on-chip peripheral capabilities. The DF6805 soft core is binary-compatible with the industry standard Motorola 68HC05 8-bit microcontroller. It can achieve the performance of 45 – 100 million instructions per second. The DF6805 has a FAST architecture that is 4.1 times faster compared to the original implementation. In the standard configuration, the core has major peripheral functions integrated on-chip. The DF6805 Microcontroller Core contains a full-duplex UART – Asynchronous Serial Communication Interface (SCI) and can be also equipped with the Synchronous Serial Peripheral Interface (SPI). The main 16-bit, free-running timer system has two input capture lines and two output-compare lines. Self-monitoring circuitry is included on-chip to protect against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP are available to preserve additional power. These modes make the DF6805 IP Core especially attractive for automotive and battery-driven applications. The DF6805 is fully customizable – delivered in the exact configuration to meet your requirements. There’s no need to pay extra for unused features and wasted silicon. It includes a fully automated test bench with a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Each DCD’s DF68XX Cores has built-in support for a proprietary Hardware Debug System called DoCD™. It is a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides a non-intrusive debugging of running applications. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, and SFRs, including user-defined peripherals, data, and program memories.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.

• TSMC
• UMC
• SK Hynix
  and others.

• FAST architecture – 4.1 times faster than the original implementation
• Software compatible with 68HC05 industry standard
• 11 times faster multiplication
• 64 bytes of System Function Registers space (SFRs)
• Up to 64K bytes of Data Memory
• Up to 64K bytes of Code Memory
• De-multiplexed Address/Data Bus to allow easy memory connection
• Two power saving modes: STOP, WAIT
• Ready pin allows Core to operate with slow program and data memories.
• Fully synthesizable
• Static synchronous design
• No internal reset generator or gated clock
• Positive edge clocking and no internal tri-states
• Scan test ready
• 1 GHz of virtual clock frequency compared to original implementation
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available