Description

DF6805 8-bit MCU IP Core – High-Performance, Fully Configurable 68HC05 Compatible

The DF6805 is an advanced 8-bit microcontroller IP Core with highly integrated on-chip peripherals, fully binary-compatible with the industry-standard Motorola 68HC05 microcontroller. Leveraging DCD’s FAST architecture, the DF6805 delivers 4.1× higher performance compared to the original 68HC05 and can achieve 45–100 million instructions per second, making it ideal for automotive, industrial, and battery-powered SoC applications.

The DF6805 is fully customizable, delivered in the exact configuration to meet your requirements. Only the needed features are included, reducing silicon usage and cost.

Key Features & Capabilities

  • Serial Interfaces: Full-duplex UART (Asynchronous Serial Communication Interface, SCI) and optional Synchronous Serial Peripheral Interface (SPI).

  • 16-bit Free-Running Timer: Includes 2 input capture lines and 2 output-compare lines.

  • Reliability & Safety: On-chip self-monitoring circuitry, COP watchdog system, and illegal opcode detection with non-maskable interrupt.

  • Power Efficiency: WAIT and STOP software-controlled low-power modes for energy-sensitive applications.

  • Customizable ADC Support: Optional external ADC controllers can be integrated for full 68HC05 compatibility.

  • Automated Validation: Delivered with a fully automated test bench and complete test set for easy SoC integration.

  • DoCD™ Debug Support: Built-in real-time hardware debugger provides non-intrusive SoC debugging, including CPU registers, program/data memory, SFRs, and user-defined peripherals.

Why DF6805?

The combination of high performance, low power, and fully integrated peripherals makes the DF6805 perfect for automotive electronics, industrial controls, battery-driven embedded systems, and other SoCs requiring a robust and configurable 8-bit MCU.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com

Key features

  • FAST architecture – 4.1 times faster than the original implementation
  • Software compatible with 68HC05 industry standard
  • 11 times faster multiplication
  • 64 bytes of System Function Registers space (SFRs)
  • Up to 64K bytes of Data Memory
  • Up to 64K bytes of Code Memory
  • De-multiplexed Address/Data Bus to allow easy memory connection
  • Two power saving modes: STOP, WAIT
  • Ready pin allows Core to operate with slow program and data memories.
  • Fully synthesizable
  • Static synchronous design
  • No internal reset generator or gated clock
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • 1 GHz of virtual clock frequency compared to original implementation
  • USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available
IP Core Architecture type Memory space DoCD UART (SCI) SPI M/S IO Ports Watchdog Timer Timer Compare / Capture Pulse accumulator READY pin Chip Selects Gatecount
DF6808 fast 64k 4 1 2/2 - 8300
DF6805 fast 64k 4 1 2/2 - 7000
D6802 legacy 64k - - - - -
D6803 legacy 64k 4 1 + - 6000
DF6802 fast fast - - - - -
DF6803 fast 64k 4 1 + - -
DF6811F fast 64k 7 1 5/4 - 14000
DF6811E fast 64k 5 1 5/4 - 12000
DF6811K fast 1M 10 3 13/6 - 21000
D68HC11E legacy 64k 5 1 5/4 - 13000
D68HC11F legacy 64k 7 1 5/4 4 13500
D68HC11K legacy 1M 10 3 13/6 4 21000

Features

DoCD Debugger

Power of Innovation is our primary target. That’s why our R&D focuses on every single IP Core detail. As a result of that concern, some unique solutions were born. One of them is the 68XX on-Chip Debugger (DoCD™), which is a complete debugging system dedicated for all 68XX Cores offered by DCD.

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DoCD Debugger

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